In a number of modern electronics systems, various transistor structures are designed to operate at, and withstand, different voltage and current levels. For example, numerous designs commonly utilize high-voltage “power” transistors in conjunction with low-voltage transistors. Generally, most designs seek to minimize the number of “power” transistors—as such components are relatively expensive and cumbersome, when compared to their low-voltage counterparts. To this end, and in order to successfully interface higher voltage transistors to their low-voltage counterparts, many designs pair high power transistor structures with some configuration of lower power sensing transistors.
Commonly, sensing transistors are configured in a manner that divides or scales down voltage or current levels across the high power transistor, such that those levels can be measured and processed with low-power, cost-efficient transistors. A voltage or current parameter across one low-power sensing transistor may then be measured or processed, as representative of a pre-determined fraction of that same parameter across the power transistor.
In the past, the level of accuracy with which such sensing approximations were made was—in some cases—marginal. At the time, however, system using such approaches may not have needed highly accurate sensing. As the demands on signal communications and processing systems have steadily increased, though, the need for greater accuracy and precision in sensing transistor arrangements has also increased.
Most conventional sensing transistor arrangements commonly involve a power transistor fabricated on the same die as one or more sensing transistors. For example, a CMOS power FET may have one or more sense FETs fabricated on the same die. In some instances, a sense FET may be physically located some distance on the die from the power FET, or it may be located directly about the perimeter thereof.
Conventionally, addressing the accuracy of sense FETs concerns matching—as closely as possible—the fabrication characteristics of a sense FET to a power FET. Even where a sense FET is fabricated around the immediate perimeter of a power FET, only a limited level of matching or accuracy can be attained. Fabrication and processing variations between the transistor structures in the center of a large power FET and a sense FET around the outer perimeter of the power FET commonly result in some nominal degree of mismatch—thereby limiting the achievable accuracy level of conventional sense FET designs. Thermal variations between the area of the sense FET and the area of the power FET can also further contribute to mismatch.
In addition to the physical considerations, there are also now a number of parametric considerations that may impact the usefulness of conventional sense transistor configurations. For example, there are a number of advanced power transistor designs that—to a certain extent—render such conventional sense transistor topologies inefficient or infeasible. These power transistor designs may be optimized for operational parameters—such as extremely low on resistance (Ron)—that make conventional divide or scale down sensing impractical.
As a result, there is a need for a system that provides highly accurate sense transistor circuitry—one that optimizes matching of sense and power transistor structures, and minimizes or obviates thermal and fabrication variations—in a versatile, cost-effective, commercially-viable manner.